1. Field of the Invention
The present invention relates to a semiconductor integrated circuit inspection method and a semiconductor integrated circuit inspection apparatus in which a test pattern generated for a semiconductor integrated circuit comprising plural transistors is input at an input terminal of the semiconductor integrated circuit and the semiconductor integrated circuit is inspected.
2. Description of Related Art
For shipment of reliable and high-quality products after pre-shipment defectives detection, semiconductor integrated circuits are tested through various types of tests (See Japanese Patent Application Laid Open No. 2000-98002 for instance.) A reliability test on a semiconductor integrated circuit includes inspection which aims at confirming the reliability of a gate oxide film of each transistor which forms the semiconductor integrated circuit. To be more specific, a test pattern for inspection of gate oxide films is generated for a semiconductor integrated circuit which needs be inspected, and with a higher voltage than a rated voltage applied upon a power source terminal of the semiconductor integrated circuit in a high-temperature environment, the generated test pattern is input at an input terminal of the semiconductor integrated circuit. The specified voltage is thus applied for a necessary amount of time upon the gate oxide film of each transistor which forms the semiconductor integrated circuit, thereby inspecting the durability of the gate oxide film of each transistor.
During the inspection, it is necessary to apply a proper voltage upon all transistors which form the semiconductor integrated circuit for a proper amount of time, and therefore, highly accurate inspection is impossible if the voltages applied upon the transistors are different or the application time varies. It is desired to generate a test pattern with which it is possible to apply an appropriate voltage upon all transistors which form the semiconductor integrated circuit for an appropriate amount of time.
However, it is difficult to grasp whether a proper voltage is applied upon each transistor which forms the semiconductor integrated circuit for a proper amount of time during the inspection above: It is difficult to grasp which level of voltage is applied upon which transistor for how long during the inspection. The difficulty of verifying whether a generated test pattern is proper or not leads to a problem that it is extremely difficult to generate a test pattern which realizes application of an appropriate voltage upon all transistors. In addition, as the circuit size of a semiconductor integrated circuit has grown, a burden of test pattern generation has increased.